\doxysection{DMA\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_d_m_a___type_def}{}\label{struct_d_m_a___type_def}\index{DMA\_TypeDef@{DMA\_TypeDef}}
\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}}
\end{DoxyCompactItemize}


\label{doc-variable-members}
\Hypertarget{struct_d_m_a___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}\index{DMA\_TypeDef@{DMA\_TypeDef}!HIFCR@{HIFCR}}
\index{HIFCR@{HIFCR}!DMA\_TypeDef@{DMA\_TypeDef}}
\doxysubsubsection{\texorpdfstring{HIFCR}{HIFCR}}
{\footnotesize\ttfamily \label{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA\+\_\+\+Type\+Def\+::\+HIFCR}

DMA high interrupt flag clear register, Address offset\+: 0x0C \Hypertarget{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}\index{DMA\_TypeDef@{DMA\_TypeDef}!HISR@{HISR}}
\index{HISR@{HISR}!DMA\_TypeDef@{DMA\_TypeDef}}
\doxysubsubsection{\texorpdfstring{HISR}{HISR}}
{\footnotesize\ttfamily \label{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA\+\_\+\+Type\+Def\+::\+HISR}

DMA high interrupt status register, Address offset\+: 0x04 \Hypertarget{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}\index{DMA\_TypeDef@{DMA\_TypeDef}!LIFCR@{LIFCR}}
\index{LIFCR@{LIFCR}!DMA\_TypeDef@{DMA\_TypeDef}}
\doxysubsubsection{\texorpdfstring{LIFCR}{LIFCR}}
{\footnotesize\ttfamily \label{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA\+\_\+\+Type\+Def\+::\+LIFCR}

DMA low interrupt flag clear register, Address offset\+: 0x08 \Hypertarget{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}\index{DMA\_TypeDef@{DMA\_TypeDef}!LISR@{LISR}}
\index{LISR@{LISR}!DMA\_TypeDef@{DMA\_TypeDef}}
\doxysubsubsection{\texorpdfstring{LISR}{LISR}}
{\footnotesize\ttfamily \label{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA\+\_\+\+Type\+Def\+::\+LISR}

DMA low interrupt status register, Address offset\+: 0x00 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
